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? 1 ? CXD2951GA-2 176 pin lflga (plastic) single chip gps lsi description the CXD2951GA-2 is a dedicated single chip lsi for the gps (global positioning system), satellite- based location measurement system. this lsi enables the configuration of a single chip system providing a cost-effective, low-power solution. compared with conventional methods, position detection time and sensitivity are substantially improved with the use of an advanced signal processing scheme. with the integration of both the radio and baseband blocks into a single cmos ic, the CXD2951GA-2 is ideal for use in automotive, cellular handset, handheld navigation, mobile computing and other location-based applications. features ? 12-channel gps receiver capable of simultaneously receiving 12 satellites reception frequency: 1575.42mhz (l1 band, ca code) reference clock (tcxo) frequency: 18.414mhz (gps, sony standard), the unique frequency of major applications is available, such as gsm and w-cdma. (optional) 13.000mhz (gsm), 14.400mhz (cdma), 16.368mhz (gps), 19.800mhz (pdc/cdma), 26.000mhz (gsm) 32 bits risc cpu (arm7tdmi) 288k-bytes program rom 72k-bytes data ram power is supplied only to 8k-byte data ram while in backup mode. system power management 1-channel uart internal rtc (real time clock) 10-bit successive approximation system a/d converter, a/d data available on nmea messages all-in-view positioning communication format: supports nmea-0183 1 pps output supports assisted-gps for cellular (optional) radio image rejection mixer vco tank if filters structure silicon gate cmos ic absolute maximum ratings supply voltage i/o iov dd ?0.5 to +4.6 v supply voltage core cv dd ?0.5 to +2.5 v supply voltage radio v dd ?0.5 to +2.5 v input voltage v i ?0.5 to +6 v output voltage v o ?0.5 to +6 v operating temperature topr ?40 to +85 c storage temperature tstg ?50 to +150 c recommended operating conditions supply voltage i/o iov dd 3.0 to 3.6 v ? under operation with internal rom, using no external expansion bus: iov dd 2.6 to 3.6 v ? under operation in backup mode: bkupiov dd 2.5 (min.) v supply voltage core cv dd 1.62 to 1.98 v supply voltage radio v dd 1.62 to 1.98 v operating temperature topr ?40 to +85 c input/output pin capacitance (baseband) input capacitance c in 9 (max.) pf output capacitance c out 11 (max.) pf i/o capacitance c i/o 11 (max.) pf e04445a49 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
? 2 ? CXD2951GA-2 performance baseband tracking sensitivity: ?152dbm (average) or less acquisition sensitivity: ?139dbm (average) or less in normal mode ?150dbm (average) or less in high sensitivity mode ? reference data using the sony's reference board when using both an antenna of 0dbi and a rf amplifier with nf 2db, 25db gain. ttff (time to first fix): time until initial position measurement after power-on with the following conditions: cold start (without both ephemeris and almanac time): 50s (average) / 60s (95% possibility) warm start (without ephemeris but with almanac time): 35s (average) / 40s (95% possibility) hot start (with both ephemeris and almanac time): 2s (minimum) / 6s (95% possibility) ? reference data with elevation angle of 5 or more and no interception environment with satellite powers ?130dbm. (not in high sensitivity mode) note) "95% possibility" means "position time with 95% possibility". positioning accuracy: 2drms: approx. 5m ? reference data with elevation angle of 5 or more and no interception environment with satellite powers ?130dbm. measurement data update time: 1s power consumption: 50mw (average) while position calculating with tracking satellites in low power mode 120mw (average) while position calculating with acquiring and tracking satellites ? reference data using the sony's reference board when the reference clock input is 18.414mhz, and its amplitude is 3.3v swing. 1pps output 1s or less precision, 1pps outputs from eclkout (pin 97). note) these values are not guaranteed, depending on the conditions. radio total gain (typ.): 100db noise figure (typ.): 8db synthesizer phase noise (typ.): ?70dbc/hz (10khz) ?80dbc/hz (100khz) pll spurious (typ.): ?45dbc (inside fosc 1.023mhz) ?55dbc (outside fosc 1.023mhz) note) these values are not guaranteed.
? 3 ? CXD2951GA-2 system block diagram rom 288kb ram 72kb timer 3ch arm7tdmi costas loop & dll 1 bit lpf bpf down converter freq. synthesizer tcxo cpu lna saw reference clock 18.414mhz (gps, sony standard) tcxo lna 1575.42mhz 1.023mhz rf/if 1575.42mhz 1.023mhz computation & control control acquisition & tracking block position calculating acquisition block acquire gps signals tracking block locking to gps signals 12ch correlations rtc i/o uart a/d x'tal 32.768khz
? 4 ? CXD2951GA-2 pin configuration (top view) 6 3 176 81 83 82 137 135 140 85 86 84 96 98 100 103 105 107 122 125 127 129 133 136 62 60 61 161 157 156 64 63 65 158 154 153 76 77 74 143 141 144 79 80 78 139 138 142 53 48 55 169 164 166 57 54 52 167 163 162 59 56 58 165 159 160 71 70 69 147 149 151 75 73 72 145 146 148 67 68 66 155 150 152 50 46 51 173 171 168 47 44 43 39 35 32 28 24 21 9 174 172 90 92 93 94 102 104 106 110 118 120 126 128 130 87 88 89 91 95 97 99 101 108 121 123 124 131 132 134 49 45 40 37 33 31 27 29 25 11 7 5 1 175 170 42 41 38 36 34 30 26 22 14 10 8 15 12 111 113 119 19 112 115 116 109 114 117 23 20 13 18 17 16 4 2 ea3 ea5 cv ss 3 ea9 iov dd 2 etest0 cv ss 2 if2gnd if1gnd test outp mixgnd lnasrc rfin 18 17 16 15 14 13 9 8 7 6 5 4 3 2 1 v u t r p n m l k j h g f e d c b a v u t r p n m l k j h g f e d c b a ea0 ea2 ea4 ea7 ea8 ea11 cv dd 2 vcom if1v cc test outn mixgnd mixgnd lnasrc mixgnd nring cv dd 4 ea1 ea6 cv dd 3 ea10 ea12 etest1 rref if2v cc testinn test outd testinp rfsub rfrref lnamat eclki cv ss 4iov dd 3 v dd vco vcode cap v ss vco eclko iov ss 3 exromi v dd cp lpfrf v ss cp eadvrb eclkout eavdpll v dd pll v ss pll lpfif evin1 eavspll evin0 etesttck tms radiosub evin3 eavsad evin2 etesttms tdi tck etest3 eavdad eadvrt etesttdi etesttint tdo bkupiov dd eclks1 eclks2 eport10 eport8 iov ss 1 eclks0 iov ss 4 excs1 eport6 eport5 eport9 exoe excs0 exwe3 eport4 eport2 eport7 iov dd 7iov ss 8 etest4 etesttdo cv dd 1cv ss 1 eccki bkupcv dd bkupcv ss trst iov dd 1 extcxo eccko bkupiov ss eoscen eport12 eport11 etcxo exwe2 iov ss 5 exwe1 ed27 ed25 ed21 ed12 ed9 ed5 ed3 ed1 erxd0 eport0 iov dd 6 eport3 exwe0 iov dd 4 ed31 ed29 ed26 ed23 iov dd 5 ed13 ed11 ed7 ed6 cv ss 6iov ss 7 etxd0 eport1 ed30 ed28 ed24 ed22 ed20 iov ss 6 ed14 ed10 iov ss 2 ea15 ea19 12 11 10 18 17 16 15 14 13 9 8 7 6 5 4 3 2 1 12 11 10 ea13 ea16 ea18 ea14 ea17 etest2 ed19 ed17 ed15 ed18 cv ss 5cv dd 5 ed16 exrs etestxrs ed8 ed4 ed2 ed0 cv dd 6 : pin 1 index.
? 5 ? CXD2951GA-2 pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 symbol eport0 eport1 eport2 eport3 eport4 eport5 eport6 eport7 eport8 eport9 eport10 eport11 eport12 iov ss 1 iov dd 1 etcxo extcxo cv ss 1 cv dd 1 trst etesttint tdo etesttdo tdi etesttdi tck etesttck tms i/o i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i/o/z i o i o o o i i i i i description i/o port 0 (with a software controllable pull-down resistor, connected to gnd with a resistor.) i/o port 1 (with a software controllable pull-down resistor, see software application note.) i/o port 2 (with a software controllable pull-down resistor, see software application note.) i/o port 3 (with a software controllable pull-down resistor, see software application note.) i/o port 4 (with a software controllable pull-down resistor, see software application note.) i/o port 5 (with a software controllable pull-down resistor, see software application note.) i/o port 6 (with a software controllable pull-down resistor, see software application note.) i/o port 7 (with a software controllable pull-down resistor, see software application note.) i/o port 8 (with a software controllable pull-down resistor, see software application note.) i/o port 9 (with a software controllable pull-down resistor, see software application note.) i/o port 10 (with a software controllable pull-down resistor, see software application note.) i/o port 11 (with a software controllable pull-down resistor, see software application note.) i/o port 12 (with a software controllable pull-down resistor, see software application note.) gnd 3.3v tcxo oscillator (frequency selectable, see software application note.) gnd 1.8v test (open, with a pull-down resistor) test test test test (open, with a pull-up resistor) test (open, with a pull-up resistor) test (open, with a pull-down resistor) test (open, with a pull-down resistor) test (open, with a pull-up resistor)
? 6 ? CXD2951GA-2 pin no. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 symbol etesttms radiosub v dd pll v ss pll v dd cp lpfif lpfrf v ss cp v dd vco v ss vco vcodecap rfsub lnamat nring rfrref mixgnd lnasrc mixgnd rfin mixgnd lnasrc mixgnd testinp testinn testoutp testoutn testoutd if1v cc if1gnd if2v cc if2gnd vcom rref cv ss 2 cv dd 2 i/o i ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description test (open, with a pull-up resistor) radio gnd pll 1.8v pll gnd charge pump 1.8v loop filter for if pll loop filter for rf pll charge pump gnd vco 1.8v vco gnd vco decap pin rf gnd lna 1.8v lna 1.8v external resistor pin mixer gnd lna gnd mixer gnd rf input mixer gnd lna gnd mixer gnd radio test (open) radio test (open) radio test radio test radio test (open) 1st if 1.8v 1st if gnd 2nd if 1.8v 2nd if gnd if common voltage external resistor pin gnd 1.8v ? radio analog pins: see page 10 to 12 for details.
? 7 ? CXD2951GA-2 pin no. symbol i/o description 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 etest0 etset1 etest2 ea19 ea18 ea17 ea16 ea15 ea14 ea13 ea12 iov ss 2 iov dd 2 ea11 ea10 ea9 ea8 cv ss 3 cv dd 3 ea7 ea6 ea5 ea4 ea3 ea2 ea1 ea0 cv ss 4 cv dd 4 eclki eclko iov ss 3 iov dd 3 eclkout exromi eavspll eavdpll i i i o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z o/z i o o/z i test (connect to gnd.) external expansion address 19 external expansion address 18 external expansion address 17 external expansion address 16 external expansion address 15 external expansion address 14 external expansion address 13 external expansion address 12 gnd 3.3v external expansion address 11 external expansion address 10 external expansion address 9 external expansion address 8 gnd 1.8v external expansion address 7 external expansion address 6 external expansion address 5 external expansion address 4 external expansion address 3 external expansion address 2 external expansion address 1 external expansion address 0 gnd 1.8v cpu clock oscillator gnd 3.3v 1pps output (effective 1s late after reset release) boot selection (low: internal rom, high: external memory/excs0) pll gnd pll 3.3v
? 8 ? CXD2951GA-2 pin no. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 symbol eavsad eadvrb evin0 evin1 evin2 evin3 eadvrt eavdad iov ss 8 etest3 etest4 iov dd 7 bkupcv ss bkupcv dd eccki eccko bkupiov ss bkupiov dd eoscen eclks0 eclks1 eclks2 iov ss 4 excs0 excs1 exoe exwe3 exwe2 exwe1 exwe0 iov ss 5 iov dd 4 ed31 ed30 ed29 ed28 ed27 ed26 i/o i i i i i i i/o/z i/o/z i o i i i i o/z o/z o/z o/z o/z o/z o/z i/o i/o i/o i/o i/o i/o description a/d converter gnd a/d converter reference input bottom a/d converter analog input 0 a/d converter analog input 1 a/d converter analog input 2 a/d converter analog input 3 a/d converter reference input top a/d converter 3.3v gnd (connect to gnd with a resistor.) (connect to gnd with a resistor.) 3.3v backup core power supply gnd backup core power supply 1.8v rtc oscillator (32.768khz) backup i/o power supply gnd backup i/o power supply 3.3v oscillator enable (h-active), see backup mode section. test (connect to gnd.) test (connect to gnd.) test (connect to gnd.) gnd external expansion chip selection 0 (program boot is enable if exromi is high.) external expansion chip selection 1 external expansion read signal external expansion write signal external expansion write signal external expansion write signal external expansion write signal gnd 3.3v external expansion data 31 (with a pull-down resistor) external expansion data 30 (with a pull-down resistor) external expansion data 29 (with a pull-down resistor) external expansion data 28 (with a pull-down resistor) external expansion data 27 (with a pull-down resistor) external expansion data 26 (with a pull-down resistor)
? 9 ? CXD2951GA-2 pin no. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 symbol ed25 ed24 ed23 ed22 ed21 ed20 ed19 ed18 ed17 ed16 cv ss 5 cv dd 5 exrs etestxrs iov ss 6 iov dd 5 ed15 ed14 ed13 ed12 ed11 ed10 ed9 ed8 ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 cv ss 6 cv dd 6 erxd0 etxd0 iov ss 7 iov dd 6 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i o/z description external expansion data 25 (with a pull-down resistor) external expansion data 24 (with a pull-down resistor) external expansion data 23 (with a pull-down resistor) external expansion data 22 (with a pull-down resistor) external expansion data 21 (with a pull-down resistor) external expansion data 20 (with a pull-down resistor) external expansion data 19 (with a pull-down resistor) external expansion data 18 (with a pull-down resistor) external expansion data 17 (with a pull-down resistor) external expansion data 16 (with a pull-down resistor) gnd 1.8v reset (l-active) test (open, with a pull-up resistor) gnd 3.3v external expansion data 15 (with a pull-down resistor) external expansion data 14 (with a pull-down resistor) external expansion data 13 (with a pull-down resistor) external expansion data 12 (with a pull-down resistor) external expansion data 11 (with a pull-down resistor) external expansion data 10 (with a pull-down resistor) external expansion data 9 (with a pull-down resistor) external expansion data 8 (with a pull-down resistor) external expansion data 7 (with a pull-down resistor) external expansion data 6 (with a pull-down resistor) external expansion data 5 (with a pull-down resistor) external expansion data 4 (with a pull-down resistor) external expansion data 3 (with a pull-down resistor) external expansion data 2 (with a pull-down resistor) external expansion data 1 (with a pull-down resistor) external expansion data 0 (with a pull-down resistor) gnd 1.8v uart (ch0) reception data (with a pull-down resistor during reset interval) uart (ch0) transmission data (with hi-z during reset interval) gnd 3.3v
? 10 ? CXD2951GA-2 radio pin description pin no. symbol 30 31 32 33 radiosub v dd pll v ss pll v dd cp description radio gnd pll 1.8v pll gnd charge pump 1.8v standard pin voltage [v] 34 5k 1k v dd cp if2v cc if2gnd v ss cp 35 1k 1k 1k v dd cp if1v cc v ss cp v dd vco v ss vco 39 if1v cc if1gnd 250 43 equivalent circuit 0 1.8 0 1.8 34 lpfif if pll loop filter connection 0.8 35 lpfrf rf pll loop filter connection 0.9 39 vcodecap capacitor connection for decoupling the vco bias circuit 0.65 36 37 38 40 42 v ss cp v dd vco v ss vco rfsub nring charge pump gnd vco 1.8v vco gnd rf gnd lna 1.8v 0 1.8 0 0 1.8 43 rfrref external resistor connection (lna, rf mixer bias) 0.1
? 11 ? CXD2951GA-2 pin no. symbol 44 45 46 mixgnd lnasrc v dd cp description mixer gnd lna gnd charge pump 1.8v standard pin voltage [v] equivalent circuit 0 0 1.8 41 lnamat lna 1.8v 1.8 47 rfin rf input ? 48 49 50 mixgnd lnasrc mixgnd mixer gnd lna gnd mixer gnd 0 0 0 47 41 if1v cc lnasrc 7k 10k 51 52 if1v cc if1gnd 200 200 if1v cc if1gnd 53 54 51 testinp radio test input pin normally leave open. ? 52 testinn radio test input pin normally leave open. ? 53 testoutp radio test output pin capacitor and resistor connection ? 54 testoutn radio test output pin capacitor and resistor connection ?
? 12 ? CXD2951GA-2 pin no. symbol description standard pin voltage [v] equivalent circuit 55 testoutd radio digital test output pin normally leave open. ? 56 57 58 59 if1v cc if1gnd if2v cc if2gnd 1st if 1.8v 1st if gnd 2nd if 1.8v 2nd if gnd 1.8 0 1.8 0 60 vcom if common voltage 1.0 61 rref external resistor connection (vco, pll, if block bias) 1.1 if2v cc if2gnd 55 if1v cc if1gnd 1k 60 40k 50k 61 6k if1v cc if1gnd
? 13 ? CXD2951GA-2 a/d converter operating conditions item supply voltage operating temperature symbol unit v c v ad ta a/d converter characteristics (v ad = 3.0 to 3.6v, ta = ?40 to +85c) item resolution channel differential linearity error (dle) integral linearity error (ile) sampling time conversion time reference input voltage (top) reference input voltage (bottom) analog input voltage current consumption symbol unit bit ch lsb lsb s s v v v ma v rt ? 2 v rb ? 3 v in ? 4 applicable pins ? 1 eavdad (pin 108) ? 2 eadvrt (pin 107) ? 3 eadvrb (pin 102) ? 4 evin[0:3] (pins 103 to 106) min. 3.0 ?40.0 ty p. 3.3 max. 3.6 +85.0 min. ?1.0 ?2.0 3 2.0 0 v rb ty p. 1.6 max. 10 4 +1.0 +2.0 11 v ad 0.7 v rt pin name eavdad ? 1 ? conditions v ad = 3.0v, v rt = 3.0v, v rb = 0.3v tcxo = 18.414mhz v ad = 3.0v
? 14 ? CXD2951GA-2 dc characteristics (iov dd = 3.0 to 3.6v, cv dd = 1.62 to 1.98v, ta = ?40 to +85c) item input voltage ? 1 output voltage ? 2 output voltage ? 3 pull-up resistor ? 4 pull-down resistor ? 5 current consumption during normal operation (via iov dd , cv dd and v dd ) ? 6 current consumption during backup operation (via bkupiov dd ) ? 7 current consumption during backup operation (via bkupcv dd ) ? 8 conditions i oh = 4ma i ol = 4ma i oh = 8ma i ol = 8ma tcxo = 18.414mhz, ta = 25c bkupiov dd = 3.6v, ta = 25c bkupiov dd = 3.6v, ta = 85c bkupcv dd = 1.98v, ta = 25c bkupcv dd = 1.98v, ta = 85c symbol v ih v il v oh1 v ol1 v oh2 v ol2 r u r d i ope i stb1 i stb2 high level low level high level low level high level low level unit v v v v v v k ? k ? ma a a a a applicable pins ? 1 pins 1 to 13, 20, 24 to 29, 64 to 66, 98, 119, 120 to 122, 133 to 148, 151, 152, 155 to 170, 173 ? 2 pins 1 to 13, 21 to 23, 97, 174 ? 3 pins 67 to 74, 77 to 80, 83 to 90, 124 to 130, 133 to 148, 155 to 170 ? 4 pins 24, 25, 28, 29, 152 ? 5 pins 1 to 13, 20, 26, 27, 133 to 148, 155 to 170, 173 ? 6 pins 15, 76, 96, 100, 108, 112, 118, 132, 154, 176 (3.3v) pins 19, 31, 33, 37, 41, 42, 56, 58, 63, 82, 92, 114, 150, 172 (1.8v) ? 7 pin 118 ? 8 pin 114 min. 2.0 ?0.3 2.4 2.4 48 40 typ. max. 5.5 0.8 0.4 0.4 110 100 1.0 1.0 15 120 60 0.2 0.2 7.5 50
? 15 ? CXD2951GA-2 item exoe to address valid exoe to excs data setup data hold min. max. 3 1 15 0 unit ns ns ns ns symbol toea toecs ta s ta h ac characteristics external expansion bus (read/32-bit mode) (cv dd = 1.62 to 1.98v, iov dd = 3.0 to 3.6v, c l = 25pf, topr = ?40 to +85c) exoe ea[19:0] excs[1:0] ed[31:0] toea toecs tas tah
? 16 ? CXD2951GA-2 extarnal expansion bus (write/32-bit mode (1-wait)) (cv dd = 1.62 to 1.98v, iov dd = 3.0 to 3.6v, c l = 25pf, topr = ?40 to +85c) tcsfav excs[1:0] ea[19:0] exwe[3:0] ed[31:0] t1 t2 t3 tcswer tcsd tcswef item excs to address valid excs to exwe excs to exwe excs to data valid min. max. 2 tsys ? 1 tsys 3 ? 2 15 unit ns ns ns ns symbol tcsfav tcswef tcswer tcsd ? tsys: arm clock cycle
? 17 ? CXD2951GA-2 backup mode the backup mode is established by setting both eoscen and exrs low. in this mode, the low power consumption can be achieved by stopping all oscillators except for rtc oscillator during the reset interval. although all registers are initialized, the sram contents in backup area are held. in order to cancel this mode (reset cancellation), set eoscen high at first and then set exrs high after the oscillation stabilization time and pll lock time have passed. it needs 100ms or more. see initialization section. osc, pll output eoscen exrs oscillation stabilization time reset normal operation normal operation ed[31:0], eport[12:0], erxd0 etxd0 excs[1:0], exwe[3:0], exoe ea[19:0], eclkout backup cv dd iov dd bkupcv dd bkupiov dd power off power off power off power off hi-z output pull-down output high output low output pll lock time (0.5ms max.)
? 18 ? CXD2951GA-2 initialization the CXD2951GA-2 is initialized by setting the reset signal exrs (pin 151) to the low level. note that internal ram is not initialized by the operation. satisfy the conditions shown below for the timing and others. 1. when turning the power on (power-on reset) v dd v dd [v] gnd exrs (pin 151) power supply, eoscen (pin 119) v dd /2 100ms or more v dd gnd v dd /2 100s or more v dd [v] exrs (pin 151) power supply, eoscen (pin 119) the power supply both 3.3v and 1.8v should turn on simultaneously, and eoscen (pin 119) should also rise simultaneously with the power supply turning on. exrs (pin 151) should rise 100ms or more after the power supply and eoscen rise. 2. initialization during operation for initialization during operation, the interior circuit except internal ram is initialized by setting the exrs (pin 151) signal to the low level for 100s or more. note that internal ram is not also initialized by the operation. at this time, the eoscen (pin 119) signal should keep the high level.
? 19 ? CXD2951GA-2 rtc crystal and tcxo in order to operate CXD2951GA-2 appropriately, the recommended characteristics of rtc crystal and tcxo is shown below. recommended characteristics of rtc crystal operating temperature ?40 to +85c nominal frequency 32.768khz frequency toler ance 20ppm frequency temperature coefficient ?0.04ppm/c 2 (max.) frequency peak temperature +25 5c frequency aging 3ppm/year recommended characteristics of tcxo operating temperature ?40 to +85c frequency tolerance 2.0ppm frequency vs. temperature 2.5ppm frequency vs. supply voltage 0.2ppm frequency vs. load 0.2ppm frequency aging 1ppm/year recommended parts rtc crystal epson fc-255 tcxo ndk sna3088b (nt5032 series)
? 20 ? CXD2951GA-2 radio block operation radio block diagram shows rf section of the chip. the signal flow starts from the rfin port (pin 47). the signal is amplified and mixed down to the first intermediate frequency (if) of 2mhz with cosine and sine wave quadrature mixers. out of band images are filtered out and the signal is again mixed down to the 2nd if of 1mhz with another set of quadrature mixers. the complex signal becomes real with the addition of real and imaginary components. the image of the 2nd if mixing is removed with the last band pass filter (bpf). the real signal is then amplified one last time and transferred to digital baseband processing unit. to have constant internal frequencies for mixing and other purposes, the supplied tcxo frequency is counted by a real time clock (rtc), and the internal pll divider is automatically set to provide correct frequency for rf mixing and baseband operation. the loop filters (rf and if) are externally connected. use parts that satisfy the required tolerance. rf digital rf analog reset clk data pllclk enable 2nd if (1mhz) a/d converter 1st if (2mhz) rfin rf local (1573mhz) if local (3mhz) lpfrf lpfif baseband bpf bpf bpf vco pll buf test bias vco pll radio block diagram
? 21 ? CXD2951GA-2 radio characteristics dc characteristics (v dd = 1.8v, ta = 25c) item supply current 1 supply current 2 symbol unit ma a i dd i ps min. 13.5 ? ty p. 17 0.1 max. 20.5 1.5 conditions active mode ? 1 power save mode ? 1 ? 1 applicable pins 31, 33, 37, 41, 42, 56, 58 ac characteristics (v dd = 1.8v, ta = 25c) item total gain image rejection ratio 2nd if filter 2.5mhz 2nd if filter 4mhz symbol unit db db db db g imrr fc fa min. 90 ? ?6 ? ty p. 100 ?35 0 ?25 max. ? ?15 4 ?15 conditions before the a/d converter image frequency = 1571.328mhz @2.5mhz normalized at 1.023mhz @4mhz normalized at 1.023mhz ? including the 50 ? matching circuit design measurement results (v dd = 1.8v, ta = 25c) item total nf iip3 p-1db input s11 lock up time c/n 100k local leak symbol unit db dbm dbm db ms dbc/hz dbm nf iip3 p1db s11 lut c/n leak min. ? ? ? ? ? ? ? ty p. 8 ?90 ?100 ?15 2.5 ?70 ?65 max. ? ? ? ? ? ? ? conditions before the 2nd if mixer before the a/d converter before the a/d converter measure the interval between reset input and if output. tcxo = 18.414mhz measure at rf input. ? including the 50 ? matching circuit
? 22 ? CXD2951GA-2 radio supplement materials (example of representative characteristics) input/output characteristic filter characteristic represented by rf frequency as x-axis (normalized at 1.023mhz) 24 10 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 22 20 18 16 14 12 10 1.6 1.8 v dd [v] input level [dbm] i dd i dd [ma] output level [dbm] iip3 10 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?130 ?120 ?125 ?115 ?105 ?110 ?100 ?95 ?90 ?85 ?80 ?75 ?70 input level [dbm] output level [dbm] 2.0 ?20 ?25 ?30 ?35 ?40 ?45 ?50 0 0.5 1.0 1.5 2.0 2.5 if frequency [mhz] image rejection ratio imrr [db] 3.0 5 0 ?10 ?5 ?25 ?20 ?15 ?30 ?35 ?40 1.570 1.571 1.572 1.573 1.574 1.575 1.576 1.577 1.578 1.579 1.580 1.581 frequency [ghz] if filter response (simulation) response [db] ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 10 100 offset frequency [khz] c/n c/n [dbc/hz] 1000 v dd = 1.8v ta = 25?c v dd = 1.8v ta = 25?c v dd = 1.8v ta = 25?c v dd = 1.8v ta = 25?c v dd = 1.8v ta = 25?c
? 23 ? CXD2951GA-2 1.2ghz 1.6ghz 1ghz 2ghz 0 +j10 +j25 +j50 +j100 ?j10 ?j25 ?j50 ?j100 25 50 100 1.8ghz 1.4ghz rfin input impedance
? 24 ? CXD2951GA-2 application circuit ic006 r1160n181b c072 0.1 c069 0.1 c077 0.1 c079 0.1 r204 22 r020 1m c067 0.1 c068 0.1 c060 0.01 c076 0.1 c082 0.1 c083 0.1 c129 0.1 c126 0.1 c125 0.1 c124 0.1 c128 0.1 c127 0.1 c088 0.1 r057 100k c090 0.1 c086 12p c085 12p x002 r056 100k r203 22 c089 0.1 c092 0.1 l024 1h c093 0.1 c094 0.1 cv dd _1.8v r028 xx r025 100k r201 xx system_reset l046 56nh l045 1h r013 470k c045 0.1 r004 10k r005 10k r202 xx r001 22 10p cn012 1 2 3 4 5 6 7 8 9 10 txd0 rxd0 rxd1 nmea/orig update reset/power down dgnd v dd (3.3v/5v) batt agnd r002 22 r063 22 r062 22 r205 47k l003 10h l051 56nh x001 l002 22h c004 22 c161 10 c013 10 c046 0.1 ic002 xx js040 0 r1124n331d c121 0.1 c059 0.1 c048 2.2 c066 10 bkupiov dd _3.3v bkupcv dd _1.8v ic005 r1124n181d c162 10 c150 10 ic003 max6364 xreset gnd reset in batt out vcc ic004 r3112q291a ic020 CXD2951GA-2 ic021 mbm29pl320 c122 0.1 1 vout nc ce 1 gnd 2 5 4 v dd 3 2 3 6 5 v dd gnd out cd 1 2 4 3 4 v dd vout eco 1 gnd 2 5 4 ce 3 vout nc ce 1 gnd 2 5 4 v dd 3 js041 0 js025 0 l040 1h c146 0.001 cl003 cl004 cl002 cl005 cl001 c147 0.01 c148 xx c166 100p c167 100p r206 1m r207 1m r200 56k ic022 njg1107kb2 1 2 3 6 5 4 c131 100p c163 xx c157 xx swf001 c134 0.001 c154 0.1 c132 39p l034 15nh l048 12nh l044 4.7nh l050 3.9nh l018 27nh l035 56nh ic024 njg1107kb2 1 2 3 6 5 4 c156 100p c159 0.001 c158 0.1 c155 1p l042 15nh l041 12nh tp001 l023 82nh l043 3.3nh l036 56nh c140 0.068 c141 3300p c142 680p c143 68p c144 0.01 c153 xx c139 0.001 c145 10p c149 0.01 js038 0 js039 0 js037 xx l004 2.7nh l039 12nh r199 2k r198 33k r197 470 c3 b1 d2 c1 d3 e2 e3 d1 f2 e1 f3 g2 g3 f1 h2 g1 h1 j1 j2 h3 k2 k1 j3 l2 k3 l1 m3 m2 l3 m1 n3 n2 p3 n1 p2 p1 r3 r1 r2 t3 t1 u1 t2 u2 u3 u4 v2 u5 v3 v4 t4 t6 v5 u6 t5 u7 v6 t7 v7 u8 t8 v8 u9 v9 t9 t10 v10 u10 t11 u11 v11 t12 u12 t13 v12 v13 u13 t14 v14 u14 v15 t15 u15 t16 v16 u16 v17 u17 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 t17 u18 r16 n17 p16 m17 n16 l17 n18 m16 m18 l16 l18 k16 k17 b16 a17 b16 a16 c15 b14 c14 a15 b13 a14 c13 a13 f17 f16 e17 d17 e16 d18 d16 c18 c16 b18 c17 b17 j17 k18 j16 j18 h16 h17 h18 g18 g17 f18 g16 e18 r17 t18 r18 p18 p17 eport0 eport1 eport2 eport3 eport4 eport5 eport6 eport7 eport8 eport9 eport10 eport11 eport12 iov ss 1 iov dd 1 etcxo extcxo cv ss 1 cv dd 1 trst etesttint tdo etesttdo tdi etesttdi tck etesttck tms etesttms radiosub v dd pll v ss pll v dd cp lpfif lpfrf v ss cp v dd vco v ss vco vcodecap rfsub lnamat nring rfrref mixgnd iov dd 4 iov ss 5 exwe0 exwe1 exwe2 exwe3 exoe excs1 excs0 iov ss 4 eclks2 eclks1 eclks0 eoscen bkupiov dd bkupiov ss eccko eccki bkupcv dd bkupcv ss iov dd 7 etest4 etest3 iov ss 8 eavdad eadvrt evin3 evin2 evin1 evin0 eadvrb eavsad eavdpll eavspll exromi eclkout iov dd 3 iov ss 3 eclko eclki cv dd 4 cv ss 4 ea0 ea1 lnasrc mixgnd rfin mixgnd lnasrc mixgnd testinp testinn testoutp testoutn testoutd if1v cc if1gnd if2v cc if2gnd vcom rref cv ss 2 cv dd 2 etest0 etset1 etest2 ea19 ea18 ea17 ea16 ea15 ea14 ea13 ea12 iov ss 2 iov dd 2 ea11 ea10 ea9 ea8 cv ss 3 cv dd 3 ea7 ea6 ea5 ea4 ea3 ea2 ea19 ea18 ea17 ea16 ea15 ea14 ea13 ea12 ea11 ea10 ea9 ea8 ea7 ea6 ea5 ea4 ea3 ea2 a4 a1 nc xwe nc xce vcc a5 a2 acc nc dw/xw vss dq30 dq17 dq1 dq0 a3 xwp nc xoe ea6 ea3 ea7 ea4 ea5 ed30 ed17 de1 ed0 nc a15 a18 dq24 vcc dq22 dq23 a6 a9 nc a14 a17 vcc dq9 vss a7 a10 nc a13 a16 a19 ea17 ea8 ea11 ea16 ea19 ea9 ea12 ea15 ea18 ed24 ed22 ed23 ed9 dq20 dq12 dq28 vss nc nc dq2 dq18 dq19 dq3 dq13 dq29 dq14 dq31/a-1 nc a0 dq16 vss vcc vcc dq15 ed20 ed12 ed28 ed2 ed18 ed19 ed3 ed13 ed29 ed14 ed31 ed16 ed15 ea2 a11 a8 dq7 vcc dq26 vss dq25 dq8 nc a12 dq21 dq6 vss dq27 dq11 dq10 nc nc nc dq5 dq4 ea13 ea10 ea14 ed7 ed26 ed25 ed8 ed21 ed6 ed27 ed11 ed10 ed5 ed4 iov dd 6 iov ss 7 etxd0 erxd0 cv dd 6 cv ss 6 ed0 ed1 ed2 ed3 ed4 ed5 ed6 ed7 ed8 ed9 ed10 ed11 ed12 ed13 ed14 ed15 iov dd 5 iov ss 6 etestxrs exrs cv dd 5 cv ss 5 ed16 ed17 ed18 ed19 ed20 ed21 ed22 ed23 ed24 ed25 ed26 ed27 ed28 ed29 ed30 ed31 ed0 ed1 ed2 ed3 ed4 ed5 ed6 ed7 ed8 ed9 ed10 ed11 ed12 ed13 ed14 ed15 ed16 ed17 ed18 ed19 ed20 ed21 ed22 ed23 ed24 ed25 ed26 ed27 ed28 ed29 ed30 ed31 c12 b12 c11 a12 b11 b10 a10 a9 b9 c10 a8 b8 c9 b7 a7 a6 b6 b5 c7 a5 c6 a4 c5 a3 a2 c4 b2 b3 c2 a11 c8 b4 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 152 153 154 155 156 157 158 159 160 162 163 164 165 166 167 168 169 170 172 173 174 175 176 151 161 171 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 89 90 96 97 98 99 100 101 102 103 104 105 106 107 108 121 122 123 124 125 126 127 128 129 130 131 132 109 110 111 112 113 114 115 116 117 118 119 120 91 92 93 94 95 a3 a4 a5 a6 a7 a8 b2 b3 b4 b5 b6 b7 b8 b9 c1 c2 c3 c4 c5 c6 c7 h4 h5 h6 h7 h8 h9 j1 j2 j3 j4 j5 j6 j7 j8 j9 k2 k3 k4 k5 k6 k7 k8 f1 e9 e8 e7 e6 e5 e4 e3 e2 e1 d9 d8 d7 d6 d5 d4 d3 d2 d1 c9 c8 h3 h2 h1 g9 g8 g7 g6 g5 g4 g3 g2 g1 f9 f8 f7 f6 f5 f4 f3 f2 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. note) the following should be guaranteed within operating temperature. r tolerance: 5% or less c tolerance: 20% or less l tolerance: 20% or less note) if a flash rom is used, the programs which are gps software, flash updater etc. required for desired operation should be written into a flash rom in advance.
? 25 ? CXD2951GA-2 radio block application circuit c076 0.1 c082 0.1 c146 0.001 cl003 cl004 cl002 cl005 cl001 c147 0.01 c148 xx c166 100p c167 100p r206 1m r207 1m r200 56k ic022 njg1107kb2 1 2 3 6 5 4 c131 100p c134 0.001 c154 0.1 c132 39p l034 15nh l044 4.7nh l050 3.9nh l035 56nh c140 0.068 c141 3300p c142 680p c143 68p c144 0.01 c153 xx c139 0.001 c145 10p c149 0.01 js038 0 js039 0 js037 xx l004 2.7nh l039 12nh r199 2k r198 33k r197 470 m3 m2 l3 m1 n3 n2 p3 n1 p2 p1 r3 r1 r2 t3 t1 u1 t2 u2 u3 u4 v2 u5 v3 v4 t4 t6 v5 u6 t5 u7 v6 t7 v7 u8 t8 v8 u9 v9 t9 t10 v10 u10 t11 u11 v11 t12 u12 t13 v12 v13 u13 t14 v14 u14 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 etesttck tms etesttms radiosub v dd pll v ss pll v dd cp lpfif lpfrf v ss cp v dd vco v ss vco vcodecap rfsub lnamat nring rfrref mixgnd lnasrc mixgnd rfin mixgnd lnasrc mixgnd testinp testinn testoutp testoutn testoutd if1v cc if1gnd if2v cc if2gnd vcom rref cv ss 2 cv dd 2 etest0 etset1 etest2 ea19 ea18 ea17 ea16 ea15 ea14 ea13 ea12 iov ss 2 iov dd 2 ea11 ea10 ea9 ea8 ea19 ea18 ea17 ea16 ea15 ea14 ea13 ea12 ea11 ea10 ea9 ea8 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 enlarged view of the previous page c139 to c147, c149, c166, c167 l004, l039, l050 r197 to r200 r206, r207 murata grm36ch series taiyo yuden hk1005 series koa rk73h series koa rk73b series tolerance: 5% c145: self-resonant frequency 2.0ghz or more tolerance: 5% l050: self-resonant frequency 2.0ghz or more tolerance: 1% tolerance: 5% parts id parts name remarks ? always use matching circuit for the rf amplifier input pin (pin 47), and match at 1.57542ghz. ? the external elements should be placed as close to the chip as possible. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
? 26 ? CXD2951GA-2 package outline unit: mm sony corporation sony code eiaj code jedec code package mass package structure organic substrate 0.4g package material terminal treatment terminal material nickel&gold plating copper 176pin lflga detail x 1.3max s s 0.2 s 0.08 0.10max p-lflga176-12x12-0.5 pin 1 index 12.0 0.1 a s 12.0 0.1 b s 0.08 x4 a b 0.5 1.75 1.75 0.5 176 ? 0.27 0.04 0.05 m s ab (0.55) (0.55) (0.55) 16 11 12 3 4 56 7 8910 121314 1718 15 a b c d e f g h j k l m n p r t u v (0.55) 0.25 x 1.2 1.2 1.2 1.2 1.0 1.0 lflga-176p-052 y detail y 0.35 3 ? 1.0 c0.3

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